Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC Tube

These dual positive-edge-triggered D-type flip-flops are designed for 2.7-V to 5.5-V VCC operation.A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to theoutputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.The SN74LV74 is available in TI"s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.The SN54LV74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV74 is characterized for operation from -40°C to 85°C.

EPIC^TM (Enhanced-Performance Implanted CMOS) 2-µ Process

Typical V_OLP (Output Ground Bounce) < 0.8 V atV_CC, T_A = 25°C

Typical V_OHV (Output V_OH Undershoot)> 2 V at V_CC, T_A = 25°C

ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015;Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17

Package Options Include Plastic Small-Outline (D), ShrinkSmall-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat(W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs