Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC T/R
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-µA Max ICC Typical tpd = 17 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible
Характеристики
| Бренд | Texas Instruments |
|---|---|
| Описание продукта | 8.75 x 4 x 1.5 mm |
| Maximum H | -4 mA |
| Bus Hold | Нет |
| Polarity | Inverting/Non-Inverting |
| Set Reset | Set/Reset |
| Number Of | 1 |
| Number Of | 2 |
| Triggering Type | Positive-Edge |
| Рабочая температура | -40 to 85 °C |
| Input Sig | Single-Ended |
| Maximum L | 4 mA |
| Number Of | 2 |
| Maximum P | 28@4.5V|25@5.5V ns |
| Maximum O | 5.5 V |
| Maximum Q | 0.004 mA |
| Output Si | Differential |
| Logic Function | D-Type |
| Number Of | 1 |
| Propagati | 50 pF |
| Minimum O | 4.5 V |
| Lead Finish | Gold |
| Supplier | SOIC |
| Max Proce | 260 |
| Typical O | 5 V |
| Msl Level | 1 |
| Schedule B | 8542390000 |
| HTSN | 8542390001 |
| Страна происхождения | Malaysia |
| Screening Level | Commercial |
SKU: SN74HCT74DR