Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC T/R
The ’AHC74 dual positive-edge-triggered devices are D-type flip-flops.A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
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- 1000-V Charged-Device Model (C101)
Характеристики
| Бренд | Texas Instruments |
|---|---|
| Описание продукта | 8.75 x 4 x 1.5 mm |
| Maximum H | -8 mA |
| Bus Hold | Нет |
| Polarity | Inverting|Non-Inverting |
| Set Reset | Set/Reset |
| Number Of | 1 |
| Number Of | 2 |
| Triggering Type | Positive-Edge |
| Рабочая температура | -40 to 85 °C |
| Input Sig | Single-Ended |
| Maximum L | 8 mA |
| Number Of | 2 |
| Maximum P | 15.4@3.3V|9.3@5V ns |
| Maximum O | 5.5 V |
| Maximum Q | 0.002 mA |
| Output Si | Differential |
| Logic Function | D-Type |
| Number Of | 1 |
| Propagati | 50 pF |
| Minimum O | 2 V |
| Lead Finish | Gold |
| Supplier | SOIC |
| Max Proce | 260 |
| Typical O | 2.5|3.3|5 V |
| Msl Level | 1 |
| Schedule B | 8542390000 |
| HTSN | 8542390001 |
| Страна происхождения | Malaysia |
| Screening Level | Commercial |
SKU: SN74AHC74DR