Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC T/R

The ’AC74 devices are dual positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

2-V to 6-V V_CC Operation

Inputs Accept Voltages to 6 V

Max t_pd of 10 ns at 5 V