Flip Flop D-Type Bus Interface Pos-Edge 3-ST 2-Element 56-Pin SSOP T/R

These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers.The "ACT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN\) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR\) input low causes the Q outputs to go low independently of the clock.A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.The 74ACT16823 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.The 54ACT16823 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16823 is characterized for operation from -40°C to 85°C

Members of the Texas Instruments Widebus^TM Family

Inputs Are TTL-Voltage Compatible

Provide Extra Data Width Necessary for Wider Address/DataPaths or Buses With Parity

Flow-Through Architecture Optimizes PCB Layout

Distributed V_CC and GND Pin Configuration MinimizesHigh-Speed Switching Noise

EPIC^TM (Enhanced-Performance Implanted CMOS) 1-µm Process

Package Options Include Plastic 300-mil Shrink Small-Outline(DL) Packages Using 25-mil Center-to-Center Pin Spacings and380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-milCenter-to-Center Pin Spacings