Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SSOP T/R

The 74LVT574; 74LVTH574 is a high-performance product designed for VCC operation at 3.3 V. This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The two sections of the device are controlled independently by the clock (pin CP) and output enable control gates. The state of each Dn input (one setup time before the LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Qn output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable controls all eight 3-state buffers independent of the clock operation. When pin output enable is LOW, the stored data appears at the outputs. When pin output enable is HIGH, the outputs are in the high-impedance OFF-state, which means they will neither drive nor load the bus.

• Inputs and outputs arranged for easy interfacing to microprocessors
• 3-state outputs for bus interfacing
• Common output enable control
• TTL input and output switching levels
• Input and output interface capability to systems at 5 V supply
• Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
• Live insertion and extraction permitted
• No bus current loading when output is tied to 5 V bus
• Power-up reset
• Power-up 3-state