Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin SOIC W Rail

The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

• Ideal for addressable register applications
• Clock enable for address and data synchronization applications
• Eight edge-triggered D-type flip-flops
• Buffered common clock