Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin SOIC T/R

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)

Typical V_OLP (Output Ground Bounce)
    <0.8 V at V_CC = 3.3 V, T_A = 25°C

Support Unregulated Battery Operation Down to 2.7 V

Buffered Clock and Direct-Clear Inputs

Individual Data Input to Each Flip-Flop

I_off Supports Partial-Power-Down-Mode Operation

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Latch-Up Performance Exceeds 500 mA Per JESD 17

ESD Protection Exceeds JESD 22

• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)