Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin SOIC T/R

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. 

’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs

’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs

Buffered Clock and Direct-Clear Inputs

Applications Include:

• Buffer/Storage Registers
• Shift Registers
• Pattern Generators

Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)