Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin SOIC N Rail

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

• Advanced oxide-isolated ion-implanted Schottky TTL process
• Pin and functional compatible with LS familycounterpart
• Typical clock frequency maximum is 80MHz
• Switching performance guaranteed over full temperature and VCC supply range