Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin PDIP Bulk
The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of CP and D0 to D3. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Standardized symmetrical output characteristics
- Specified from–40 ? to +125 ?
- Complies with JEDEC standard JESD 13-B
Характеристики
| Бренд | Nexperia |
|---|---|
| Описание продукта | 19.5 x 6.48 x 3.2 mm |
| Maximum H | -4.2 mA |
| Bus Hold | Нет |
| Polarity | Inverting|Non-Inverting |
| Set Reset | Master Reset |
| Number Of | 4 |
| Number Of | 4 |
| Triggering Type | Positive-Edge |
| Рабочая температура | -40 to 125 °C |
| Input Sig | Single-Ended |
| Number Of | 1 |
| Maximum P | 160@5V|70@10V|50@15V ns |
| Maximum O | 15 V |
| Maximum Q | 0.004 mA |
| Output Si | Differential |
| Logic Function | D-Type Bus Interface |
| Number Of | 4 |
| Propagati | 50 pF |
| Minimum O | 3 V |
| Lead Finish | Gold |
| Supplier | PDIP |
| Max Proce | 260 |
| Typical O | 3.3|5|9|12 V |
| Schedule B | 8542390000 |
| HTSN | 8542390001 |
| Страна происхождения | United States |
| Screening Level | Automotive |
SKU: HEF40175BP,652