Flash Programmable System Device 80-Pin LQFP Tray

The PSD family of memory systems for microcontrollers (MCUs) brings In-System Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. PSD devices integrate optimized macro cell logic architecture. The macro cell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

• Dual bank Flash memories
  • 4 Mbit of Primary Flash memory (8 uniform sectors, 32K x 16)
  • 256 Kbit Secondary Flash memory with 4 sectors
  • Concurrent operation: read from one memory while erasing and writing the other
• 64 Kbit SRAM
• PLD with macrocells
  • Over 3000 gates of PLD: CPLD and DPLD
  • CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)
  • DPLD - user defined internal chip select decoding
• 7 L/O ports with 52 I/O pins
  • 52 individually configurable I/O port pins that can be used for the following functions:
  • MCU I/Os
  • PLD I/Os
  • Latched MCU address output
  • Special function l/Os
  • l/O ports may be configured as open-drain outputs
• In-system programming (ISP) with JTAG
  • Built-in JTAG compliant serial port allows full-chip In-System Programmability
  • Efficient manufacturing allow easy product testing and programmingUse low cost FlashLINK cable with PC
• Page register
  • Internal page register that can be used to expand the microcontroller address space by a factor of 256
  • Programmable power management
• High endurance
  • 100,000 Erase/write c ycles of Flash memory
  • 1,000 Erase/WRITE Cycles of PLD
  • 15 Year Data Retention
• Single supply voltage
  • 5V ±10%
• Memory speed
  • 70ns Flash memory and SRAM access time
• Packages are ECOPACK®