FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 9 32-Pin PLCC

The CY7C4261 are high speed, low power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71 are pin compatible to the CY7C42X1 synchronous FIFO family. The CY7C4261 can be cascaded to increase FIFO width. Programmable features include almost full/almost empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

• High speed, low power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261)
• 0.5 micron CMOS for optimum speed and power
• High speed 100 MHz operation (10 ns read/write cycle times)
• Low power - ICC = 35 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, full, half full, and programmable almost empty and almost full status flags
• TTL compatible
• Output enable pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free running 50% duty cycle clock inputs
• Width expansion capability
• 32-pin PLCC and 32-pin TQFP
• Pin compatible density upgrade to CY7C42X1 family
• Pin compatible density upgrade to IDT72201/11/21/31/41/51
• Pb-free packages available