Ethernet CTLR Single Chip 10Mbps/100Mbps

The Intel IXF440 Multiport Ethernet Controller includes eight independent 10/100 Mbps Ethernet MACs and interfaces directly to MII standard PHYs or SYM 100BASE-TX physical devices. The IXF440 handles SNMP and RMON management counter sets, accessible through a generic CPU interface, which is also used for mode programming. Each MAC includes two 256-byte independent FIFOs for packet transmit and receive. All the packets are transferred onto a high-performance, common FIFO interface, or IX Bus. The IXF440 is fully compatible with IEEE standards, including Fast Ethernet and flow-control support. It is implemented in a low-power 3.3 V CMOS device within a 352-BGA package.

• Integration
  • Eight Ethernet 10/100 Mbps MAC ports
  • Onchip scrambler, descrambler, and PCS functions for 100BASE-X connection
  • Handles SNMP and RMON counters
• IX Bus
  • Supports a 4 Gbps high bus bandwidth
  • Variable bus speed of 25 to 66 MHz operational, and from 16 MHz for testing
  • Interfaces a 64-bit bus with a 32-bit optional mode
  • Supports concurrent unidirectional 32-bit buses for transmit and receive in split IX Bus mode
  • Provides transmit- and receive-independent 256-byte FIFOs for each of the eight ports
  • Offers a generic slave FIFO interface
  • Supports little or big endian byte ordering
  • Supports transmit and receive byte alignment
  • Supports receive packet fragmentation on byte boundaries (replay feature)
  • Provides programmable transmit and receive bus thresholds
  • Appends packet status to received packet
• Performance
  • Allows status register access without interrupting packet transfer
  • Enables early address filtering ability, with packet header preprocessing and VLAN detection ability
  • Offers retry or ignore options following packet transmission errors
  • Supports automatic retransmission following excessive collisions
  • Provides programmable automatic discard of badly received packets such as runts, CRC errors, and too long packets
• Operation
  • Enables independent 10 or 100 Mbps port operation
  • Provides full-duplex support
  • Enables standard flow-control functionality in full-duplex mode
  • Offers backpressure logic capability in half-duplex mode
  • Interfaces to standard MII connections
  • Supports 10BASE-T, 100BASE-TX, 100BASE-T4, and 100BASE-FX connections
  • Provides programmable CRC generation and removal
  • Allows backoff limit programming
  • Provides full collision support, including jamming, backoff, and automatic retransmission
  • Complies with IEEE 802.3 Standard
• CPU Interface
  • Supports fully programmable independent ports through a dedicated generic CPU port
  • Enables interrupt programming
• Device
  • Optimized for switch, bridge, and router applications
  • Includes internal and external loopback capabilities
  • Provides software reset support
  • Supports JTAG boundary scan
  • Low-power 3.3 V and 5 V tolerant CMOS device
  • 352-BGA package