Dual-channel LVCMOS Clock Divider

The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A and B Dividers can be cascaded to give a maximum divide of 669510. The ICS674-01 supports the ICS673 PLL Building Block and enables the user to build a full custom PLL synthesizer.

• Packaged in 28-pin SSOP (150 mil body)
• Pb (lead) free package, RoHS compliant
• General purpose programmable divider
• Supports ICS673 PLL Building Block
• User determines the divide by setting input pins
• Pull-ups on all select inputs
• Includes one 7-bit Divider for OUTA
• Includes one 9-bit Divider and one selectable Post Divider for OUTB
• Industrial temperature range available
• 25 mA drive capability at TTL levels
• Advanced, low power CMOS process
• Operating voltage of 3.3 V or 5 V