DRAMs Parts and Modules

ISSI"s 256Mb DDR2 SDRAM uses a double-data-ratearchitecture to achieve high-speed operation. Thedouble-data rate architecture is essentially a 4n-prefetcharchitecture, with an interface designed to transfer twodata words per clock cycle at the I/O balls.

• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6 supported
• Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and reduced strength options
• On-die termination (ODT)