DRAMs Parts and Modules

The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V Vdd/ Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS (Vdd = 1.8V) compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.

• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access and precharge
• Programmable CAS latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, and Full Page
• Programmable Burst Sequence:
• Sequential and Interleave
• Auto Refresh (CBR)
• TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Arrays Self Refresh): 1/16, 1/8, 1/4, 1/2, and Full
• Deep Power Down Mode (DPD)
• Driver Strength Control (DS): 1/4, 1/2, and Full
• Configurations: 16M x 16
• Power Supply: Vdd/Vddq = 1.8V
• Packages: BGA (54)
• Temperature Range: Industrial (-40 °C to 85 °C)