DRAMs Parts and Modules

ISSI"s 64Mb Synchronous DRAM IS42/45S32200L isorganized as 524,288 bits x 32-bit x 4-bank for improvedperformance.ThesynchronousDRAMsachievehigh-speeddata transfer using pipeline architecture.

• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length: (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 16ms (A2 grade) or 64ms (Commercia, Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command