DRAM Module SDRAM 256Mbyte 168UDIMM

The MT18LSDT3272AY is high-speed, CMOS dynamic random access 256MB, 512MB, and 1GB memory modules organized in a x72 ECC configuration. SDRAM modules use 4-bank SDRAM devices with a synchronous interface (all signals are registered on the positive edge of clock signal CK). Read and write accesses to SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank; A0–A11 select the device row for the 256MB module; A0–A12 select the device row for the 512MB and 1GB modules). The address bits registered coincident with the READ or WRITE command are used to select the starting device column location for the burst access. SDRAM modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed device row precharge that is initiated at the end of the burst sequence. SDRAM modules use an internal pipelined architecture. Precharging one device bank while accessing one of the other three device banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs and outputs are LVTTL compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic device column-address generation, the ability to interleave between device banks to hide precharge time, and the capability to randomly change device column addresses on each clock cycle during a burst access.

• 168-pin, PC133-compliant registered dual in-line memory module (RDIMM)
• Phase-lock loop (PLL) clock driver to reduce loading
• Uses 133 MHz SDRAM components
• Supports ECC error detection and correction
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB (128 Meg x 72)
• VDD = +3.3V
• Fully synchronous; all signals are registered on the positive edge of the PLL clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full page
• Single rank
• Auto precharge option
• Auto and self refresh modes: 15.625µs (1GB) or 7.81µs (256MB, 512MB) maximum periodic refresh interval
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts