DRAM Module SDRAM 128Mbyte 168RDIMM Tray

The MT9LSDT1672 and MT9LSDT3272 are high speed CMOS, dynamic random-access, 128MB and 256MB memory modules organized in x72 configurations. These modules use internally configured quadbank SDRAMs with a synchronous interface (all signals are registered on the positive edge of clock signals CK0). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank; A0-A11 for 128MB/A0-A12 for 256MB, select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. These modules are designed to operate in 3.3V, low power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

• JEDEC-standard 168-pin, dual in-line memory module (DIMM)
• PC133- and PC100-compliant
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• ECC-optimized pinout
• 128MB (16 Meg x 72), 256MB (32 Meg x 72)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive edge of PLL clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• AutoPrecharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms refresh (128MB - 4,096 cycles; 256MB - 8,192cycles)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)