DRAM Module DDR4 SDRAM 8Gbyte 284UDIMM

High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from DDR4 SDRAM"s use of an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8 n -bit- wide, four-clock data transfer at the internal DRAM core and eight corresponding n -bit- wide, one-half-clock-cycle data transfers at the I/O pins. DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and pro- vide precise crossing points to capture input signals.

• DDR4 functionality and operations supported as defined in the component data sheet
• 260-pin, small-outline dual in-line memory module (SODIMM)
• Fast data transfer rates: PC4-2400, PC4-2133, or PC4-1866
• 8GB (1 Gig x 64)
• VDD= 1.20V (TYP)
• VPP= 2.5V (TYP)
• VDDSPD= 2.2–3.6V
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die VREFDQ generation and calibration
• Dual-rank
• Onboard I2C serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus