DRAM Module DDR4 SDRAM 32Gbyte 288LRDIMM

High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from DDR4 SDRAM"s use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins.DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

• DDR4 functionality and operations supported
• 288-pin, command/address/control-registered, data-buffered, load-reduced dual in-line memory module (LRDIMM)
• Fast data transfer rates: PC4-2400 or PC4-2133
• 32GB (4 Gig x 72)
• VDD = 1.20V (NOM)
• VPP = 2.5V (NOM)
• VDDSPD = 2.5V (NOM)
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die internal, adjustable VREFDQ generation
• Quad-rank, using 8Gb TwinDie™ DDR4
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Multiplexed command and address bus
• Terminated control, command, and address bus