DRAM Module DDR2 SDRAM 8Gbyte 240FBDIMM

The MT36HTS1G72 DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 4GB and 8GB memory modules organized in a x72 configuration. These DDR2 SDRAM modules use internally configured 8-bank (1Gb, 2Gb TwinDie, or 4Gb TwinDie) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edge aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

• 240-pin, registered dual in-line memory module (RDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, or PC2-5300
• Densities
  • 4GB (512 Meg x 72)
  • 1Gb stacked (HTJ)
  • 2Gb TwinDie™ (HTS)
  • 8GB (1 Gig x 72)
  • 4Gb TwinDie
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Dual rank
• Multiple internal device banks for concurrent operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts