DRAM Module DDR2 SDRAM 8Gbyte 240FBDIMM

Micron’s FBDIMM devices adhere to the currently proposed industry specifications for FBDIMMs. The following specifications contain detailed information on FBDIMM design, interfaces, and theory of operation and are listed here for the system designers’ convenience. FBDIMM Design Specification – pending JEDEC approval. FBDIMM: Architecture and Protocol – JESD206. FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20. Design for Test, Design for Validation (DFx) Specification. Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C. This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from the channel behind an AMB on the FBDIMM. Memory device capacity remains high, and total memory capacity scales with DDR2 SDRAM bit density. As shown in the System Block Diagram, the FBDIMM channel provides a communication path from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM devices from the channel enhances the communication path and significantly increases the reliability and availability of the memory subsystem.

• DDR2 functionality and operations supported as defined in the component data sheet
• 240-pin, fully buffered dual in-line memory module (FBDIMM)
• Fast data transfer rates: PC2-6400, PC2-5300, or PC2-4200
• 8GB (1 Gig x 72)
• 3.2 Gb/s, 4 Gb/s, or 4.8 Gb/s link transfer rates
• High-speed, 1.5V differential, point-to-point link between the host controller and advanced memory buffer (AMB)
• Fault-tolerant; can work around a bad bit lane in each direction
• High-density scaling with up to eight FBDIMM devices per channel
• SMBus interface to AMB for configuration register access
• In-band and out-of-band command access
• Deterministic protocol
  • Enables memory controller to optimize DRAM accesses for maximum performance
  • Delivers precise control and repeatable memory behavior
• Automatic DDR2 SDRAM bus and channel calibration
• Transmitter de-emphasis to reduce intersymbol interference (ISI)
• Mixed-signal built-in self-test (MBIST) and interrupt-driven built-in self-test (IBIST) test functions
• Transparent mode for DRAM test support
• VDD = VDDQ = 1.8V for DRAM
• VREF = 0.9V SDRAM command and address termination
• VCC = 1.5V for AMB
• VDDSPD = 3–3.6V for AMB and EEPROM
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Dual-rank
• Supports 95°C operation with 2X refresh