DRAM Module DDR SDRAM 512Mbyte 184UDIMM Tray

The MT9VDDT6472AY is high-speed, CMOS dynamic random access 128MB, 256MB, and 512MB memory modules organized in a x72 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

• 184-pin, registered dual in-line memory module (RDIMM)
• Tall and standard height PCB modules
• Fast data transfer rates: PC2100 or PC2700
• 128MB (16 Meg x 72), 256MB (32 Meg x 72), and 512MB (64 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR) 2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 15.625µs (128MB) and 7.8125µs (256MB and 512MB) maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum compatibility
• Gold edge contacts