DRAM Module DDR SDRAM 1Gbyte 200SODIMM

The MT18VDDF12872H is a high-speed, CMOS, dynamic random access, 1GB memory module organized in a x72 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs.DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

• 200-pin, small-outline dual in-line memory module (SODIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V (-40B: VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received with data—that is, source-synchronous data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent operation
• Selectable burst lengths (BL) 2, 4, or 8
• Autoprecharge option
• Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum compatibility
• Dual rank
• Gold edge contacts