DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin TF-BGA T/R

The AS4C4M32S SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C4M32S provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth.

• Clock rate: 143/166 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 1M word x 32-bit x 4-bank
• Programmable Mode
  • CAS Latency: 2, or 3
  • Burst Length: 1, 2, 4, 8, or full page
  • Burst Type: Sequential & Interleave
  • Burst-Read-Single-Write
  • Burst stop function
• Individual byte controlled by DQM0-3
• Operating temperature range –
• Commercial (0 ~ 70°C)
• Industrial (-40 ~ 85°C)
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• Single 3.3V power supply
• Interface: LVTTL
• 86-pin 400 mil plastic TSOP II package - Pb free and Halogen free