DPLL 64-Pin CABGA Tray
DPLL 64-Pin CABGA Tray
- Supports the requirements of ITU-T G.8262 forsynchronous Ethernet Equipment slave Clocks(EEC option 1 and 2)
- Supports the requirements of Telcordia GR-1244Stratum 3 and GR-253, ITU-T G.812 and G.813
- Supports ITU-T G.823, G.824 and G.8261 for2048 kbit/s and 1544 kbit/s interfaces
- Frequency, Phase and Time Synchronization overIP, MPLS and Ethernet Packet Networks
- Frequency accuracy performance for WCDMAFDD,GSM, LTE-FDD and femtocellapplications, with target performance less than± 15 ppb
- Frequency performance for ITU-T G.823 andG.824 synchronization interface, as well as G.8261 PNT EEC, PNT PEC and CES interfacespecifications
- Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA andCDMA2000 applications with target performance less than ± 1 µs phase alignment.
- Time Synchronization for UTC-traceability and GPS replacement.
- Meets the SONET/SDH jitter generation requirements up to OC-48/STM-16
- Synchronizes to telecom reference clocks (2 kHz,N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz,62.5 MHz, 125 MHz)
- Programmable output synthesizer generates telecom clock frequencies from any multiple of8 kHz up to 100 MHz
- Generates standard SONET/SDH clock rates(e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz,155.52 MHz, 622.08 MHz) or Ethernet clock rates(e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz,312.5 MHz) for synchronizing Gigabit EthernetPHYs
- DPLL that is configurable through a serial interface
- Client reference switching between multiple Servers
- Client holdover when Server packet connectivity islost
Характеристики
| Бренд | Microchip |
|---|---|
| Supplier | CABGA |
| Рабочая температура | -40 to 85 °C |
| Category | DPLL |
| Описание продукта | 9 x 9 x 1.26 mm |
| Schedule B | 8542310000 |
| HTSN | 8542310001 |
| Lead Finish | Tin/Silver/Copper |
| Msl Level | 3 |
SKU: ZL30342GGG2