Display Interface Bridge 81-Pin BGA

TC358767AXBG is a bridge device that enables video streaming from a Host (application or baseband processor) over MIPI DSI or DPI link to drive Display Port display panels. TC358767AXBG also supports audio streaming from the host via I²S interface to the Display panels. TC358767AXBG provides a low power bridge solution to efficiently translate MIPI DSI or DPI transfers to Display Port transfers. As the Display Port uses fewer wires compared to other existing display panel standards, it simplifies the LCD connectivity. The effect of using TC358767AXBG is to enable existing baseband devices supporting DSI or DPI streaming to connect to new panels supporting Display Port interface and also to connect to existing panels over longer distance using Display Port adaptors at far-end. TC358767AXBG can interface to up to two independent devices.

• Translates MIPI DSI/DPI Link video stream from Host to DisplayPort Link data to external displaydevices
• The inputs are driven by a DSI Host with 4-Data Lanes, upto1 Gbps/lane or DPI Host with16/18/24 bit interface upto154 MHz parallel clock
• Supports HDCP Digital Content Protection version 1.3 (DisplayPort amendment Rev1.1)
• Embeds audio information from the I²S port into the DisplayPort data stream
• The output Interface consists of a DisplayPort Tx with a 2-lane Main Link and AUX-Ch
• Register Configuration: From DSI link or I²C interface
• Interrupt to host to inform any error status or status needing attention from Host
• Internal test pattern (color bar) generator for DP o/p testing without any video (DSI/DPI) i/p
• Debug/Test Port: I²C Slave
• DSI Receiver
  • MIPI DSI: v1.01 / MIPI D-PHY: v0.90 Compliant
  • Up to four Data Lanes with Bi-direction support on Data Lane 0
  • Maximum speed at 1 Gbps/lane
  • Supports Burst as well as Non-Burst Mode Video Data
  • Video data packets are limited to one row per Hsync period
  • Supports video stream packets for video data transmission
  • Supports generic long packets for accessing the chip"s register set
  • Video input data formats:
  • RGB-565, RGB-666 and RGB-888
  • New DSI V1.02 Data Type Support: 16-bit YCbCr422
  • Interlaced video mode is not supported
• DPI Receiver
  • Up to 16 / 18 / 24 bit parallel data interface
  • Maximum speed at 154 MPs (MPixel per sec)
  • Video input data formats: RGB-565, RGB-666 and RGB-888
  • Only Progressive mode supported
  • Shutdown support (can be used in non-DPI mode also)
• I²S Audio Interface: Supports one I²S port for audio streaming from the host to TC358767AXBG
  • Supports slave mode (BCLK, LRCLK andover-sampling clock input from Host)
  • Supports sampling frequencies of 32, 44.1, 48, 88.2, 96, 176.4 and 192 kHz
  • Supports up to 2 audio channels
  • Supports 16, 18, 20 or 24bits per sample
  • Optionally inserts IEC60958 status bits and preamble bits per channel
• I²C Interface:
  • I²C slave interface for chip register set accessenabled using a boot-strap option
  • I²C compliant slave interface support for normal(100 kHz) and fast mode (400 kHz).