Development Kit For B4420 Baseband System-on-chip (SoC) Device

QorIQ Qonverge B4420 multicore system-on-chip (SoC) architecture is designed for high-performance wireless infrastructure applications. It provides ultra-high-performance for carrier-grade metrocell and microcell base station platforms supporting various wireless standards including WCDMA (HSPA/HSPA+), FDD-LTE, TDD-LTE and LTE-Advanced including 3GPP LTE Rel. 10/11. This multicore SoC includes four programmable cores, two 64-bit Power Architecture cores and two cores based on a StarCore flexible vector processor (FVP) and high throughput, low latency hardware accelerators for Layer-1, Layer-2 and Transport to enable highly optimized processing for the radio processing chain from PHY to Transport layers.

Core Complex

• Two e6500 dual-thread cores built on Power Architecture® technology up to 1.6 GHz with AltiVec 128-bit SIMD engines
• Two SC3900FP Fixed/Floating-point DSP cores built on StarCore® technology up to 1.2 GHz, eachdelivering 38.4 GMacs/Core for Fixed Point or 19.2 GFlops/Core for Floating Point.

Accelerators and Memory Controllers

• Queue Manager and Buffer Manager for simplified sharing of network interfaces and hardware accelerators and management of buffer pools
• Datapath Acceleration Architecture for packet parsing, classifying and distribution
• Multi-accelerator platform engine for baseband (MAPLE-B) for LTE, LTE-Advanced and WCDMA (HSPA/HSPA+)
• DDR3/3L SDRAM 1.6 GHz 64-bit memory controllers with ECC and interleaving support with attached 512 KB L3 cache
• Integrated security acceleration (SEC 5.3)
• Trust architecture secure boot
• Enhanced serial peripheral interfaces (eSPI)
• Enhanced secure digital host controller (eSD/eMMC)
• Four I²C controllers
• Integrated flash controller supporting NAND and NOR flash and general SRAM

Basic Peripherals and Interconnect

• Four Aurora trace interfaces
• Four UART controller
• CoreNet – Internal non-blocking switch fabric for full cache coherent system
• USB 2.0 controller
• JTAG - Test Access Port (TAP) and Boundary Scan Architecture compliant with IEEE® Std. 1149.1 and 1149.6
• GPIOs
• 32-bit timers

Networking and Antenna interfaces

• High speed interfaces multiplexed into 8 SerDes 10G ports
  • Three Ethernet Interfaces supporting 2.5G/1G with IEEE 1588.2 support
  • Four CPRI 4.2 controllers running at up to 9.8G
  • Four lanes PCI Express® v2.0 controllers at up to 5G

Package

• Package – FC-PBGA, 33 mm x 33 mm, 1020 pins, 1 mm pitch, Pb-free