Decoder/Demultiplexer Single 1-to-4 240-Pin EBGA

The EV10CS140 is a monolithic high speed-demultiplexer, used to lower a 10-bit data stream of up to 3 Gsps guaranteed rate by a selectable 4 or 2 ratio (a 1:8 ratio might be achieved by interleaving two DMUXes).The DMUX is a companion chip designed to fit perfectly with all of e2v’s high speed ADCs and is capable of tracking the ADC’s output sampling rate over all operating frequency and temperature ranges. Thanks to its LVDS buffers, this DMUX can easily be interfaced with standard high-speed FPGAs (100O differentially terminated).The EV10CS140 has the same pinout and footprint as e2v’s AT84CS001 DMUX. No re-design efforts are required to use this low-power DMUX.

• High-speed ADC Family Companion Chip
• 10-bit Data
• Additional 11th Bit in Simultaneous Mode (Example: for Out-of-Range Bit)
• Staggered or Simultaneous Data Outputs
• Selectable 1:4 or 1:2 Demultiplexed Digital LVDS Outputs
• Power Consumption: 2.20 W in 1:4 DMUX Ratio 1.95 W in 1:2 DMUX Ratio
• Power Supplies: VCCD = 3.3V (Digital), VPLUSD = 2.5V (Outputs)
• LVDS Compatible Differential Data and Clock Inputs (100O Terminated)
• LVDS Compatible Differential Data and Data Ready Outputs
• Selectable Active Edge for Output Clocks: Only Rising: DR Mode Rising and Falling: DR/2 Mode
• Clock Input in CLK/2 Mode (Active on Rising and Falling Edge)
• Checker Board Data Frame Generator (BIST)
• Power Management (Sleep Mode)
• EBGA240 (Enhanced Ball Grid Array) Package
• Fine Tuning of Input Clock Path Delay Compensation of External Data and Clock Path Misalignements and Skews Once Tuned, Setting is Valid Over Full Operating Frequency and Over Specified Temperature Range