Counter/Divider Single 7-Bit Binary UP 14-Pin PDIP Bulk

The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

• Tolerant of slow clock rise and fall time
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Specified from -40 °C to +85 °C
• Complies with JEDEC standard JESD 13-B