Counter/Divider Single 3-Bit Binary UP 8-Pin SO T/R

The HC/HCT6323A are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT6323A are oscillators designed for quartz crystal combined with a programmable 3-state counter, a 3-state output buffer and an overriding asynchronous master reset. With the two select inputs S1 and S2 the counter can be switched in the divide-by-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The oscillator is designed to operate either in the fundamental or third overtone mode depending on the crystal and external components applied. On-chip capacitors minimize external component count for third overtone crystal applications. The oscillator may be replaced by an external clock signal at input X1. In this event the other oscillator pin (X2) must be floating. The counter advances on the negative-going transition of X1. A LOW level on master reset resets the counter, stops the oscillator and sets the output buffer in the 3-state condition. master reset can be left floating since an internal pull-up resistor will make the master reset inactive. In the HCT version, the master reset input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.

• 8-pin space saving package
• Programmable 3-stage ripple counter
• Suitable for over-tone crystal application up to 50 MHz (VCC =5V ± 10%)
• 3-state output buffer
• Two internal capacitors
• Recommended operating range for use with third overtone crystals 3 to 6 V
• Oscillator stop function
• Output capability: bus driver ? (15 LSTTL)
• ICC category: MSI.