Counter/Divider Single 14-Bit Binary UP Counter 16-Pin SOIC T/R
The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typ. 35 MHz at VDD = 15 V). It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
- High speed operation
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Standardized symmetrical output characteristics
- Specified from-40 °C to +85 °C
- Complies with JEDEC standard JESD 13-B
Характеристики
| Бренд | Nexperia |
|---|---|
| Supplier | SOIC |
| Number Of | 1 |
| Screening Level | Automotive |
| Lead Finish | Gold Over Nickel Palladium |
| Msl Level | 1 |
| Описание продукта | 10(Max) x 4(Max) x 1.45(Max) |
| Parallel | Нет |
| Number Of | 1 |
| Direction Type | Uni-Directional |
| Operation Mode | UP Counter |
| Maximum Q | 0.08 mA |
| Propagati | 50 pF |
| Maximum O | 15 V |
| Max Proce | 260 |
| Рабочая температура | -40 to 85 °C |
| Logic Function | Counter/Divider |
| Maximum P | 210@5V|95@10V|70@15V ns |
| Minimum O | 3 V |
| Triggering Type | Negative-Edge |
| Number Of | 12 |
| Number Of | 14 |
| Typical O | 3.3|5|9|12 V |
| Terminal | Нет |
| Schedule B | 8542390000 |
| HTSN | 8542390001 |
| Страна происхождения | Thailand |
| Reset Type | Asynchronous |
| Type Prod | Binary |
SKU: HEF4020BT-Q100J