Counter Single 14-Bit Binary UP 16-Pin CDIP Tube

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of fO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

Onboard Oscillator

Common Reset

Negative Edge Clocking

Fanout (Over Temperature Range)

• Standard Outputs . . . . 10 LSTTL Loads
• Bus Driver Outputs . . . . 15 LSTTL Loads

Wide Operating Temperature Range . . . –55°C to 125°C

Balanced Propagation Delay and Transition Times

Significant Power Reduction Compared to LSTTL Logic ICs

HC Types

• 2V to 6V Operation
• High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

HCT Types

• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
• CMOS Input Compatibility, I_l = 1µA at V_OL, V_OH