Communication Controller 44-Pin LCC

The SAB 82526 is a High-Level Serial Communication Controller compatible to the SAB 82526 HSCC with extended features and functionality (HSCX). The SAB 82526 is pin and software compatible to the SAB 82526, realizing one HDLC channel (channel B). The HSCX has been designed to implement high-speed communication links using HDLC protocols and to reduce the hardware and software overhead needed for serial synchronous communications. Due to its 8-bit demultiplexed adaptive bus interface it fits perfectly into every Siemens/Intel or Motorola 8- or 16-bit microcontroller or microprocessor system. The data through-put from/to system memory is optimized transferring blocks of data (usually 32 bytes) by means of DMA or interrupt request. Together with the storing capacity of up to 64 bytes in on-chip FIFO’s, the serial interfaces are effectively decoupled from the system bus which drastically reduces the dynamic load and reaction time of the CPU. The HSCX directly supports the X.25 LAPB, the ISDN LAPD, and SDLC (normal response mode) protocols and is capable of handling a large set of layer-2 protocol functions independently from the host processor.

• Two independent full-duplex HDLC channels (SAB 82526: one channel)
  • On chip clock generation or external clock source
  • On chip DPLL for clock recovery for each channel
  • Two independent baudrate generators (SAB 82526: one baudrate generator)
  • Independent time-slot assignment for each channel with programmable time-slot length (1-256 bit)
• Different modes of data encoding
• Modem control lines (RTS, CTS, CD)
• Support of bus configuration by collision resolution
• Programmable bit inversion
• Transparent receive/transmit of data bytes without HDLC framing
• Continuous transmission of 1 to 32 bytes possible
• Data rate up to 4 Mbit/s
• Various types of protocol support depending on operating mode
  • Auto-mode
  • Non-auto mode
  • Transparent mode
• Handling of bit oriented functions in all modes
• Support of LAPB/LAPD/SDLC/HDLC protocol in auto-mode (I- and S-frame handling)
• Modulo 8 or modulo 128 operation
• Programmable time-out and retry conditions
• Programmable maximum packet size checking
• 64 byte FIFO’s per channel and direction
• Storage capacity of up to 17 short frames in receive direction
• Efficient transfer of data blocks from/to system memory by DMA or interrupt request
• 8-bit demultiplexed or multiplexed bus interface
• Intel or Motorola type µP interface