Clock Generation Chip 20-Pin SOIC

IDT’s family of high-performance, low additive phase noise buffers is the ideal choice for use in designs where a clean frequency source is critical to a system’s operation and performance. IDT fan-out buffers feature fully differential internal architecture, reducing jitter caused by inherent common-mode noise rejection and improving output skew. The differential circuitry is constant-current and therefore injects less noise into system power supplies than single-ended solutions, reducing EMI compliance concerns. These buffers are typically used for clock distribution on wireless infrastructure designs of radio boards where low phase noise is required. IDT’s buffers are ideal for space-constraint designs by offering small footprint packaging as well as integrating the input termination network for differential signals.

• Wide selection of differential output buffers
• Optimized for low additive phase noise
• Fast output rise fall/time (as low as 100ps)
• Low-skew outputs
• Accept LVDS, LVPECL, HSTL, CML inputs
• Support small packages (e.g. VFQN 3x3 to 5x5mm)
• Support integrated input termination networks for differential signals