Clock Fanout Buffer 8-OUT 20-Pin SOIC T/R

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input.The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC341 is characterized for operation from 0°C to 70°C.

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications

TTL-Compatible Inputs and Outputs

Distributes One Clock Input to Eight Outputs

Distributed V_CC and Ground Pins Reduce Switching Noise

High-Drive Outputs (-48-mA I_OH, 48-mA I_OL)

State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation

Packaging Options Include Plastic Small-Outline (DW) Packages