Clock Fanout Buffer 6-OUT 16-Pin SOIC T/R

The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control (T\/C) inputs, various combinations of true and complementary outputs can be obtained. The output-enable (OE ) input is provided to disable the outputs to a high-impedance state.The CDC391 is characterized for operation from -40°C to 85°C.

Low Output Skew for Clock-Distribution and Clock-GenerationApplications

TTL-Compatible Inputs and Outputs

Distributes One Clock Input to Six Clock Outputs

Polarity Control Selects True or Complementary Outputs

Distributed V_CC and GND Pins Reduce Switching Noise

High-Drive Outputs (-48-mA I_OH, 48-mAI_OL)

State-of-the-Art EPIC-IIB^TM BiCMOS DesignSignificantly Reduces Power Dissipation

Packaged in Plastic Small-Outline Package