Clock Fanout Buffer 4-OUT 28-Pin Tray

The PI6CDBL402B is a PCIe 3.0 complaint high-speed,low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator.It is backward compatible with PCIe 1.0 and 2.0 specification. Phase jitter filter for PCIe 3.0/2.0/1.0 application Low power consumption with independent output power supply 1.8V-3.3V Low skew<60ps Low cycle-to-cycle jitter - 45ps(typ.) @100MHz < 1 ps additive RMs phase jitter Output Enable for all outputs Programmable PLL Bandwidth 100MHz PLL Mode operation 1 - 400 MHz Bypass Mode operation 3.3V Operation Packaging (Pb-free and Green): 28-pin TSSOP (L28)