Clock Divider Buffer 2-OUT 8-Pin SOIC N Rail

The MC100LVEL33 is an integrated div by 4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple LVEL33"s in a system. The V pin, an internally generated voltage supply, is available to this device only. For single-ended inputconditions, the unused differential input is connected toV as a switching reference voltage.V may also rebias AC coupled inputs. When used, decoupleV and V via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used,V should be left open.

• 630ps Propagation Delay
• 4.0 GHz Typical Maximum Frequency
• ESD Protection: >4 KV HBM, >200 V MM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V_CC= 3.0 V to 3.8 V with V_EE= 0 V
• NECL Mode Operating Range: V_CC= 0 V with V_EE= -3.0 V to -3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
  For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
• Transistor Count = 130 devices
• Pb-Free Packages are Available