CESoP Processor 552-Pin BGA Tray

The ZL50114 family of CESoP processors are highly functional TDM to Packet bridging devices. The ZL50114 provides both structured and unstructured circuit emulation services over packet (CESoP) for up to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also supports unstructured T3 and E3 streams. The circuit emulation features in the ZL50114 family supports the ITU Recommendations Y.1413 and Y.1453, as well as the CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay Alliance. The ZL50114 also supports IETF RFC4553 and RFC5086. The ZL50114 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. An externally supplied clock may also be used to drive the TDM interface of the ZL50114. The ZL50114 incur very low latency for the data flow, thereby increasing QoS when carrying voice services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. The ZL50114 is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting them out the packet interfaces using a variety of protocols. The ZL50114 supports a range of different packet switched networks, including Ethernet VLANs, IP and MPLS.

• Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across a packet network
• Grooming capability for Nx64 Kbps trunking
• Supports ITU-T Recommendation Y.1413 and Y.1453
• Supports IETF RFC4553 and RFC5086
• Supports MEF8 and MFA 8.0.0
• Structured, synchronous CESoP with clock recovery
• Unstructured, asynchronous CESoP, with integral per stream clock recovery
• Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports
• H.110, H-MVIP, ST-BUS backplanes
• Up to 1024 bi-directional 64 Kbps channels
• Direct connection to LIUs, framers, backplanes
• Dual reference Stratum 4 and 4E DPLL for synchronous operation
• Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces
• Flexible 32 bit host CPU interface (Motorola PowerQUICC™ compatible)
• On-chip packet memory for self-contained operation, with buffer depths of over 16 ms
• Up to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms