Bus XCVR Single 8-CH 3-ST 20-Pin SOIC T/R

These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH245 is characterized for operation from -40°C to 85°C.

State-of-the-ArtEPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per JESD 17

Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C

I_off and Power-Up 3-State Support Hot Insertion

High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package