Buffer/Line Driver 2-CH Non-Inverting 3-ST CMOS 8-Pin SSOP T/R

The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE>) input is high. To ensure the high-impedance state during power up or power down, OE> should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Qualified for Automotive Applications

Supports 5-V V_CC Operation

Inputs Accept Voltages to 5.5 V

Max t_pd of 4.3 ns at 3.3 V

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C

Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C

I_off Supports Partial-Power-Down Mode Operation

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II