Buffer/Line Driver 2-CH Inverting 3-ST CMOS 8-Pin SSOP T/R

This dual buffer driver is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Available in the Texas Instruments NanoFree Package

Supports 5-V V_CC Operation

Inputs Accept Voltages to 5.5 V

Max t_pd of 4.6 ns at 3.3 V

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C

Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C

I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection

Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

ESD Protection Exceeds JESD 22

• 2000-V Human-Body Model (A114-A)
• 1000-V Charged-Device Model (C101)