Audio Codec 81-Pin DSBGA T/R

The TWL6041 is an audio codec with a high level of integration providing analog audio codec functions for portable applications, as shown in . The device contains multiple audio analog inputs and outputs, as well as microphone biases and accessory detection. The device is connected to the OMAP 4 host processor through a proprietary PDM interface for audio data communication enabling partitioning with optimized power consumption and performance. Multichannel audio data is multiplexed to a single wire for downlink (PDML) and uplink (PDMUL). The OMAP4 device provides the TWL6041 device with five PDM audio-input channels (DL0–DL4). Channels DL0–DL3 are connected to four parallel DAC channels multiplexed to stereo headphone (HSL, HSR), stereo speaker (HFL, HFR), and earpiece (EAR) or stereo line outputs (AUXL, AUXR). The stereo headphone path has a low-power (LP) mode operating from a 32-kHz sleep clock to enable more than 100 hours of MP3 playback time. Very-high dynamic range of 104 dBA is achieved when using the system clock input and DAC path high-performance (HP) mode. Class-AB headphone drivers provide a 1-Vrms output and are ground centered for capless connection to a headphone, thus enabling system size and cost reduction. The earpiece driver is a differential class-AB driver with 2-Vrms capability to a typical 32-O load or 1.4-Vrms to a typical 16-O load. Stereo speaker path has filterless class-D outputs with 1.5-W capability per channel. Additionally, the 4-O load is supported. For output-power maximization, supply connection to an external boost is supported. Speaker drivers also support hearing aid coil loads. For vibrator and haptic feedback support, the TWL6041 device has two PWM channels with independent input signals from DL4 or I2C. Vibra drivers are differential H-bridge outputs, enabling fast acceleration and deceleration of vibra motor. An external driver for a hearing aid coil or a piezo speaker requiring high voltage can be connected to line outputs. The TWL6041 supports three differential microphone inputs (MMIC, HMIC, and SMIC) and a stereo line-input (AFML, AFMR) multiplexed to two parallel ADCs. The PDM output from the ADCs is transmitted to the OMAP4 processor through UL0 and UL1. AFML, AFMR inputs can also be looped to analog outputs (LB0, LB1). Two LDOs provide a voltage of 2.1 V to bias analog microphones (MBIAS and HBIAS). The maximum output current is 2 mA for each analog bias, allowing up to two microphones on one bias. Two LDOs provide a voltage of 1.8 V to 1.85 V to bias digital microphones (DBIAS1 and DBIAS2). One bias generator can bias several digital microphones at the same time, with a total maximum output current of 10 mA.

Four Audio Digital-to-AnalogConverter (DAC) Channels

Stereo Capless HeadphoneDrivers

• Up to 104-dB DR
• Power Tune for Performance and Power Consumption Tradeoff

Stereo 8 O, 1.5 W perChannel Speaker Drivers also with 4-O Support Capability

Differential EarpieceDriver

Stereo Line-Out

Two Audio Analog-to-DigitalConverter (ADC) Channels

• 96-dBA SNR

Four Audio Inputs:

• Three Differential Microphone Inputs
• Stereo Line-In and FM Input

Two Vibrator and Haptics FeedbackChannels

• Differential H-bridge Drivers

Two Low-Noise Analog Microphone BiasOutputs

Two Digital Microphone BiasOutputs

Analog Low-Power Loop from Line-in to Headphone and SpeakerOutputs

Dual Phase-Locked Loops (PLLs) for Flexible ClockSupport:

• 32-kHz Sleep Clock Input for System Low-Power Playback Mode
• 12-, 19.2-, 26-, and 38.4-MHz System Clock Input

Accessory Plug and Unplug Detection, AccessoryButton Press Detection

Integrated PowerSupplies:

• Negative Charge Pump for Capless Headphone Driver
• Two Low Dropout Voltage Regulators (LDOs) for High Power Supply Rejection Ration (PSRR)

I²CControl

Thermal Protection:

• Host Interrupt

PowerSupplies:

• Analog: 2.1 V
• Digital I/O: 1.8 V
• Battery: 2.3 V–5.5 V

Package3.8-mm × 3.8-mm 81-Pin WCSP