ATA8515 Monolithic RF Transceiver Evaluation Kit

The ATA8515 is a highly integrated, low-power UHF ASK/FSK RF transceiver with an integrated AVR microcontroller. The ATA8515 is partitioned into three sections; an RF front end, a digital baseband and the low-power 8-bit AVR microcontroller. The product is designed for the ISM frequency bands in the ranges of 310MHz to 318MHz, 418MHz to 477MHz and 836MHz to 956MHz. The external part count is kept to a minimum due to the very high level of integration in this device. By combining outstanding RF performance with highly sophisticated baseband signal processing, robust wireless communication can be easily achieved. The receive path uses a low-IF architecture with an integrated double quadrature receiver and digitized IF processing. This results in high image rejection and excellent blocking performance. The transmit path uses a closed loop fractional-N modulator with Gauss shaping and pre-emphasis functionality for high data rates. In addition, highly flexible and configurable baseband signal processing allows the transceiver to operate in several scanning, wake-up and automatic self-polling scenarios. For example, during polling the IC can scan for specific message content (IDs) and save valid telegram data in the FIFO buffer for later retrieval. The device integrates two receive paths that enable a parallel search for two telegrams with different modulations, data rates, wake-up conditions, etc. The ATA8515 implements a flexible service configuration concept and supports up to 15 channels. The channels are grouped into five service configurations with three channels each. Three service configurations are located in the EEPROM. Two service configurations are located in the SRAM to allow on-the-fly modifications during IDLE Mode via SPI commands or application software. The application software is located in the Flash for ATA8510. Highly configurable and autonomous scanning capability enables flexible polling scenarios with up to 15 channels. The configuration of the transceiver is stored in a 1024byte EEPROM. The SPI interface enables external control and device reconfiguration.

• AVR® microcontroller core with 1Kbyte SRAM and 24Kbyte RF library in firmware
• ATA8515: No user memory — RF library in firmware only
• Supported frequency ranges
  • Low-band 310MHz to 318MHz, 418MHz to 477MHz
  • High-band 836MHz to 956MHz
  • 315.00MHz/433.92MHz/868.30MHz and 915.00MHz with one 24.305MHz crystal
• Low current consumption
  • 9.8mA for RXMode (low-band), 1.2mA for 21ms cycle three-channel polling
  • 9.4mA/13.8mA for TXMode (low-band, Pout = 6dBm/10dBm)
• Typical OFF Mode current of 5nA (maximum 600nA at VS = 3.6V and T = 85°C)
• Programmable output power –12dBm to +14.5dBm (0.4dB step)
• Supports the 0dBm class of ARIB STD-T96
• ASK shaping to reduce spectral bandwidth of modulated PA output signal
• Input 1dB compression point
  • –48dBm (full sensitivity level)
  • –20dBm (active antenna damping)
• Programmable channel frequency with fractional-N PLL
  • 93Hz resolution for low-band
  • 185Hz resolution for high-band
• FSK deviation ±0.375kHz to ±93kHz
• FSK sensitivity (Manchester coded) at 433.92MHz
  • –108.5dBm at 20Kbit/s ?f = ±20kHz BWIF = 165kHz
  • –111dBm at 10Kbit/s ?f = ±10kHz BWIF = 165kHz
  • –114dBm at 5Kbit/s ?f = ±5kHz BWIF = 165kHz
  • –122.5dBm at 0.75Kbit/s ?f = ±0.75kHz BWIF = 25kHz
• ASK sensitivity (Manchester coded) at 433.92MHz
  • –110.5dBm at 20Kbit/s BWIF = 80kHz
  • –125dBm at 0.5Kbit/s BWIF = 25kHz
• Programmable Rx-IF bandwidth 25kHz to 366kHz (approximately 10% steps)
• Blocking (BWIF = 165kHz): 64dBc at frequency offset = 1MHz and 48dBc at 225kHz
• High image rejection: 55dB at 315MHz/433.92MHz and 47dB at 868.3MHz/915MHz without calibration
• Supported data rate in buffered mode 0.5Kbit/s to 80Kbit/s (120Kbit/s NRZ)
• Supports pattern-based wake-up and start of frame identification
• Flexible service configuration concept with on-the-fly (OTF) modification (in IDLE Mode) of SRAM service parameters
  • Each service consists of
  • One service-specific configuration part
  • Three channel-specific configuration parts
  • Three service configurations are located in EEPROM
  • Two service configurations are located in SRAM and can be modified via SPI or embedded application software
• Digital RSSI with very high relative accuracy of ±1dB thanks to digitized IF processing
• Programmable clock output derived from crystal frequency
• 1024byte EEPROM data memory for transceiver configuration
• SPI interface for Rx/Tx data access and transceiver configuration
• 500Kbit SPI data rate for short periods on SPI bus and host controller