Applications Processor

The i.MX50 applications processors are multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX50 processors are Freescale Energy Efficiency Solutions products. The i.MX50 is optimized for portable multimedia applications and features Freescale’s advanced implementation of the ARM Cortex-A8 core, which operates at speeds as high as 1 GHz. The i.MX50 provides a powerful display architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). Additionally, the i.MX50 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, and displays.

• MMU, L1 instruction cache, and L1 data cache
• Unified L2 cache
• 800 MHz or 1 GHz target frequency of the core (including NEON, VFPv3, and L1 cache)
• NEON coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite) coprocessor supporting VFPv3 The memory system consists of the following components:
• Level 1 cache:
  • Instruction (32 Kbyte)
  • Data (32 Kbyte)
• Level 2 cache:
  • Unified instruction and data (256 Kbyte)
• Level 2 (internal) memory:
  • Boot ROM, including HAB (96 Kbyte)
  • Internal multimedia/shared, fast access RAM (128 Kbyte)
• External memory interfaces:
  • 16/32-bit DDR2-533, LPDDR2-533, or LPDDR1-400 up to a total of 2 GByte
  • 8-bit NAND SLC/MLC Flash with up to 100 MHz synchronous clock rate and up to 32-bit hardware ECC for 1 Kbyte block size
  • 16/32-bit NOR Flash with a dedicated 16-bit muxed-mode interface. I/O muxing logic selects EIMv2 port as primary muxing at system boot.
  • 16-bit PSRAM, Cellular RAM
  • Managed NAND, including eMMC up to rev 4.4 The i.MX50 introduces a next generation system bus fabric architecture that aggregates various sub-system buses and masters for access to system peripherals and memories. The various bus-systems and components are as follows:
• 64-bit AXI Fabric (266 MHz
  • This bus-fabric is the SoCs central bus aggregation point.
  • Provides access to all slave targets in the SoC:
  • ROM (ROMCP)
  • On-chip RAM (OCRAM)
  • External DRAM (DRAM MC)
  • External static RAM (EIM)
  • Interrupt controller (TZIC)
  • Decode into the AHB MAX crossbar second level AHB fabric.
  • Provides arbitration to the following masters in the system:
  • ARM CPU complex
  • Pixel processing pipeline (ePXP)
  • Electrophoretic display controller (EPDC)
  • eLCDIF LCD display controller
  • DCP Crypto engine
  • BCH ECC engine
  • MAX AHB crossbar
  • GPU 2D
  • SDMA
  • USBOH1 (USB OTG and host controller complex)
  • FEC Ethernet controller
• MAX AHB crossbar (133 MHz)
  • This connects the various AHB bus sub-segments in the system and provides decode into the following slaves:
  • IP-Bus 1 (66 MHz)
  • This bus segment contains peripherals accessible by the ARM core and without DMA capability
  • IP-Bus 2 (66 MHz)
  • This bus segment contains peripherals accessible by the ARM core and without DMA capability
  • APBH DMA bridge (133 MHz)
  • The APBH DMA bridge is a master to the MAX for its memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing peripheral access to many of the high-speed IP blocks on the i.MX50.
• IP-Bus 3 (66 MHz)
  • This third peripheral bus segment contains peripherals accessible by the ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be accessed by the ARM CPU through IP-Bus 1 and SPBA.
• Quality of service controller (QoSC)
  • This provides both soft and dynamic arbitration/priority control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and EPDC to provide dynamic priority control, based on real-time metrics. The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption, while freeing up the CPU core for other tasks. The i.MX50 incorporates the following hardware accelerators:
• GPU2Dv1
  • 2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance