Applications Processor 529-Pin TEBGA II Tray

The i.MX53 processor features ARM Cortex-A8 core, which operates at clock speeds as high as 800 MHz. It provides DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800 DRAM memories. The flexibility of the i.MX53 architecture allows for its use in a wide variety of applications. As the heart of the application chipset, the i.MX53 processor provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, hard drive, camera sensors, and dual displays.

• MMU, L1 instruction and L1 data cache
• Unified L2 cache
• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3
• TrustZone The memory system consists of the following components:
• Level 1 cache:
  • Instruction (32 Kbyte)
  • Data (32 Kbyte)
• Level 2 cache:
  • Unified instruction and data (256 Kbyte)
• Level 2 (internal) memory:
  • Boot ROM, including HAB (64 Kbyte)
  • Internal multimedia/shared, fast access RAM (128 Kbyte)
  • Secure/non-secure RAM (16 Kbyte)
• External memory interfaces:
  • 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
  • 32-bit LPDDR2
  • 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
  • 8/16-bit NOR Flash, PSRAM, and cellular RAM.
  • 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
  • 8-bit Asynchronous (DTACK mode) EIM interface.
  • All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot.
  • Samsung OneNAND and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode) The i.MX53xD system is built around the following system on chip interfaces:
• 64-bit AMBA AXI v1.0 bus-used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
• 32-bit AMBA AHB 2.0 bus-used by the rest of the bus master peripherals operating at 133 MHz.
• 32-bit IP bus-peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz. The i.MX53xD makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks. The i.MX53xD incorporates the following hardware accelerators:
• VPU, version 3-video processing unit
• GPU3D-3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance, 256 Kbyte RAM memory
• GPU2D-2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
• IPU, version 3M-image processing unit
• ASRC-asynchronous sample rate converter The i.MX53xD includes the following interfaces to external devices:
• Hard disk drives:
  • PATA, up to U-DMA mode 5, 100 MB/s
  • SATA II, 1.5 Gbps
• Displays:
  • Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two interfaces may be active at once.
  • Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example, UXGA at 60 Hz).
  • LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports up to 85 MP/s (for example, WXGA at 60 Hz) each.
  • TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).
• Camera sensors:
  • Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency.
• Expansion cards:
  • Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port supporting 832 Mbps (8-bit, eMMC 4.4).
• USB
  • High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY
• Miscellaneous interfaces:
  • One-wire (OWIRE) port