Applications Processor 529-Pin TEBGA II T/R

The MCIMX53xA (i.MX53xA) automotive infotainment processor represents Freescale Semiconductor’s advanced multimedia and power-efficient implementation of the ARM Cortex-A8 core with a high degree of functional integration, aimed at the growing automotive infotainment, telematics, HMI, and display-based cluster markets. This device includes 3D and 2D graphics processors, 1080i/p video processing, and dual display, and provides a variety of interfaces. The i.MX53xA processor features ARM Cortex-A8 core, which operates at clock speeds as high as 800 MHz. It provides DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800 DRAM memories. This device is well suited for graphics rendering for HMI, navigation, high performance speech processing with large databases, video processing and display, audio playback, and many other applications. The flexibility of the i.MX53xA architecture allows for its use in a wide variety of applications. As the heart of the application chipset, the i.MX53xA processor provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, hard drive, camera sensors, and dual displays.

• MMU, L1 instruction and L1 data cache
• Unified L2 cache
• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3
• TrustZone The memory system consists of the following components:
• Level 1 cache:
  • Instruction (32 Kbyte)
  • Data (32 Kbyte)
• Level 2 cache:
  • Unified instruction and data (256 Kbyte)
• Level 2 (internal) memory:
  • Boot ROM, including HAB (64 Kbyte)
  • Internal multimedia/shared, fast access RAM (128 Kbyte)
  • Secure/non-secure RAM (16 Kbyte)
• External memory interfaces:
  • 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
  • 32-bit LPDDR2
  • 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
  • 8/16-bit NOR Flash, PSRAM, and cellular RAM.
  • 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
  • 8-bit Asynchronous (DTACK mode) EIM interface.
  • All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot.
  • Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode) The i.MX53xA system is built around the following system on chip interfaces:
• 64-bit AMBA AXI v1.0 bus-used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
• 32-bit AMBA AHB 2.0 bus-used by the rest of the bus master peripherals operating at 133 MHz.
• 32-bit IP bus-peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz. The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks. The i.MX53xA incorporates the following hardware accelerators:
• VPU, version 3-video processing unit
• GPU3D-3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance, 256 Kbyte RAM memory
• GPU2D-2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
• IPU, version 3M-image processing unit
• ASRC-asynchronous sample rate converter The system supports efficient and smart power control and clocking:
• Power gating SRPG (State Retention Power Gating) for ARM core and Neon
• Support for various levels of system power modes
• Flexible clock gating control scheme
• On-chip temperature monitor
• On-chip oscillator amplifier supporting 32.768 kHz external crystal
• On-chip LDO voltage regulators for PLLs